The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC design and material have produced generations of ICs having smaller and more complex circuits than the previous generations. In the course of IC evolution, functional density has increased, while the geometry size (e.g., technology node) has decreased. This scaling down of the fabrication process provides benefits such as increasing production efficiency. However, the scaling down has also increased the complexity of IC processing. For the advances in technology node and functional density to be realized, developments in IC fabrication are also needed.
One such advance was in the introduction of copper interconnects and damascene processing to form the interconnect structure. A typical IC requires multiple levels of metal interconnections for connecting the semiconductor devices. Performance of ICs is critically dependent upon the quality and reliability of these interconnections. Using copper as an interconnect material has advantages such as a lower relative resistive coefficient and better electro-migration performance. However, processing of copper is difficult for example, the patterning processes typical of aluminum interconnects were insufficient. Thus, the damascene procedure was developed where a trench is provided in a dielectric layer, which is subsequently filled with copper to form an interconnect. However, typical damascene processes may also provide for challenges during their fabrication such as damage of the surrounding dielectric layer, adequate filling of the trench with copper (e.g., without the presence of gaps or voids), barrier or liner layer damage, and other known issues. Thus, it is desired to have improvements in the area of formation of conductive interconnects for ICs.